1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of integrated circuits, and, more particularly, to the formation of highly scaled transistors having ultra-shallow PN junctions for enhancing device performance.
2. Description of the Related Art
The fabrication of integrated circuits requires the formation of a large number of circuit elements, such as transistors, on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently one of the most promising approaches, due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer, typically a silicon layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed close to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers, and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region is a dominant factor determining the performance of MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, renders the channel length an important design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One major problem in this respect is the development of enhanced photolithography and etch strategies to reliably and reproducibly create circuit elements of critical dimensions, such as the gate electrode of the transistors, for a new device generation. Moreover, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions in order to provide low sheet and contact resistivity in combination with a desired channel controllability. For example, the vertical position of the PN junctions with respect to the gate insulation layer also represents a critical design criterion in view of leakage current control and gate controllability, since reducing the channel length may usually also require reducing the depth of the drain and source regions with respect to the interface formed by the gate insulation layer and the channel region, thereby requiring sophisticated implantation techniques. When forming extremely shallow drain and source regions, appropriate pre-amorphization implantation processes are typically performed to enhance the performance of the subsequent implantation process for introducing the actual dopants for defining the drain and source regions. Upon re-crystallizing the pre-amorphized portions, however, crystalline defects may be generated.
In still other approaches for enhancing the performance of sophisticated transistor devices, strain may be induced in the channel region of the transistor by re-crystallizing the amorphized portions in the presence of a stress layer formed above the transistor area. Also in this case, undue crystalline defects may be created, as will be described in more detail with reference to FIGS. 1a-1c. 
It should be appreciated that any statements regarding the position of layers or other features are to be understood as relative position information, wherein a respective substrate is to be considered as a reference. For example, a “vertical” direction is a direction perpendicular to the substrate under consideration. Similarly, a “horizontal” direction is substantially parallel to the substrate surface. A first feature is located “above” a second feature, when the latter one is positioned closer to the substrate.
FIG. 1a schematically shows a semiconductor device 100 comprising a substrate 101, such as a silicon substrate, which may have formed thereon a buried insulating layer 102, above which is formed a crystalline silicon layer 103. Moreover, the semiconductor device 100 comprises a gate electrode 104 formed above the silicon layer 103 and separated therefrom by a gate insulation layer 105. Moreover, a liner 106, for instance comprised of silicon dioxide, may be conformally formed on the gate electrode 104 and the silicon layer 103. The semiconductor device 100 is exposed to an ion implantation process 108 which may be designed such that a region 112 of the silicon layer 103 located adjacent to the gate electrode 104 is substantially amorphized. Furthermore, a doped region 107 may be formed within the layer 103 and may comprise any appropriate doping species that is required for the specific transistor to be formed in combination with the gate electrode 104. The depth of the region 107 may range from several nanometers to 20 nanometers, depending on the overall configuration of the transistor still to be formed. Generally, the depth of the region 107 may be correlated with the gate length, i.e., the horizontal dimension of the gate electrode 104, and the characteristics of the gate insulation layer 105.
A typical process flow for forming the semiconductor device 100 may comprise the following processes. After forming or providing the substrate 101 having formed thereon the buried insulating layer 102 and the silicon layer 103, appropriate implantation sequences may be performed so as to establish a desired vertical dopant profile within the layer 103, which, for convenience, is not shown in FIG. 1a. Thereafter, any appropriate isolation structures (not shown), such as shallow trench isolations or the like, may be formed. Next, an appropriate dielectric material may be formed by deposition and/or oxidation followed by the deposition of an appropriate gate electrode material, wherein both layers may then be patterned on the basis of sophisticated photolithography and etch techniques. Subsequently, the liner 106 may be formed on the basis of well-established plasma enhanced chemical vapor deposition (PECVD) techniques. Depending on the process requirements and strategy, the liner 106 may act as an offset spacer and a screening layer for the formation of the doped region 107 on the basis of well-established implantation techniques. Furthermore, prior to forming the doped region 107, which may comprise a P-type dopant or an N-type dopant, depending on whether a P-channel transistor or an N-channel transistor is to be formed, an amorphization implantation process 108 may be performed in order to reduce channeling effects during the formation of the regions 107, thereby increasing the accuracy of the vertical position and dimension of respective portions of drain and source regions still to be formed. For this purpose, an appropriate dose and energy for an implant species under consideration may be selected on the basis of well-established recipes, thereby forming the substantially amorphized regions 112. For example, xenon, germanium or other heavy ions are suitable candidates for the amorphization implantation 108. Thereafter, a spacer layer may be formed above the semiconductor device 100, wherein, in some approaches, the corresponding spacer layer may exhibit a specified type of intrinsic stress, such as tensile or compressive stress. After the deposition of the layer or after a subsequent patterning of the spacer layer into respective sidewall spacers on the basis of anisotropic etch techniques, in some approaches, an anneal process may be performed in order to re-crystallize the substantially amorphized regions 112, while, in other approaches, respective “deep” drain and source regions may be formed, followed by a common anneal process.
FIG. 1b schematically shows the semiconductor device 100 after the completion of the above-described process sequence, in which a sidewall spacer 109, which may have a high intrinsic stress, may be formed on sidewalls of the gate electrode 104, while the substantially amorphized regions 112 are substantially re-crystallized and are now indicated as 112A. If the preceding anneal process has been performed on the basis of a highly stressed spacer layer or spacer 109, the re-crystallized regions 112A are re-grown in a strained state, thereby also creating a respective strain 110 in a channel region 115 located below the gate electrode 104. In other cases, the re-grown regions 112A may be formed as substantially non-strained regions. Thereafter, the semiconductor device 100 may be subjected to further manufacturing processes for completing the transistor element.
FIG. 1c schematically shows the semiconductor device 100 with an additional spacer element 111 formed adjacent to the spacer 109 and with respective “deep” drain and source regions 113 formed within the silicon layer 103 and also partially within the region 112A or the region 112, when the respective re-crystallization anneal process has not yet been performed. The device 100 may be formed in accordance with well-established processes, such as further implantation sequences, on the basis of the spacer element 111 in order to obtain the required dopant profile for the drain and source regions 113.
Consequently, an efficient technique for the creation of the shallow region 107 may be obtained. During the operation of the device 100, however, a significant increase in leakage current may be observed, which is believed to be caused by crystalline defects 114, which may also be referred to as “zipper defects,” and which may represent a source for reducing the minority charge carrier lifetime, thereby possibly significantly contributing to an increase of leakage current.
Although the approach described with respect to FIGS. 1a-1c provides extremely shallow PN junctions for N-channel transistors and P-channel transistors, here the increased crystalline defects may occupy a significant fraction of the active device region responsible for the overall transistor performance, thereby rendering the conventional technique less attractive for the formation of sophisticated transistor devices.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.